A policing device is proposed in which a plurality of parallel police processors (PP1, PP2) are included each of which implements a Modified Virtual Scheduling Algorithm and is so able to derive for a cell for which it is activated by an enabling circuit (EC) a conformance signals (CS1, CS2). An arbitration module (AM) generates from the latter signals, a plurality of which may be provided per cell of the input ATM stream (IN), a discard signal (DS) indicating wether or not such a cell may be inserted into an output stream (OUT) by a discard circuit (DC) as well as feedback signals (FS1, FS2) which indicate to a corresponding processor whether or not to carry out an already prepared update of a predicted arrival time used in the above mentioned algorithm.;The architecture of the present policing device is very generic in that it allows implementation of any policing method by straightforwardly adapting the arbitration module and the enabling circuit.
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