Re-layout manner of the semiconductor integrated circuit and records the re-layout program of the semiconductor integrated circuit the media

摘要

PROBLEM TO BE SOLVED: To reduce a short circuit of a wiring in an area as much as possible, and reduce the processing time required for re-layout. ;SOLUTION: An area near a wiring short circuit portion is set (step S101), and a virtual terminal position on a boundary area is set (step S102). A cell layout position is optimized while the density of wiring in the area is estimated in detail from the virtual terminal position (step S104), and re-wiring is carried out in the area (step S105). Thus, the chip layout is completed. By carrying out strip-off and re-wiring in the area near the wiring short circuit portion at the same time as the change of the cell layout in the area, reduction in TAT at the time of layout design is realized.;COPYRIGHT: (C)1998,JPO