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INTEGRATED CIRCUIT DESIGN FOR SIGNAL INTEGRITY, AVOIDING WELL PROXIMITY EFFECTS

机译:信号完整性的集成电路设计,避免了良好的接近效应

摘要

A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.
机译:一种用于设计用于信号完整性的集成电路(IC)的方法,系统和程序产品。本发明对IC设计进行信号完整性分析。识别在IC设计未通过信号完整性分析的情况下引起信号完整性故障的任何场效应晶体管(FET);并修改故障FET的边缘,该边缘比阱边缘的阈值距离更短。本发明消除了用于确定由于良好的邻近效应而引起信号完整性故障的设备的手动,迭代过程。

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