Flip-flop for a ternary counter and divisor based on ternary and quaternary logic links first and second register-storage flip-flops to a ternary wheel gate for detecting a timing signal

摘要

Four different electric voltage levels are each applied to create a 0-to-3 logical number. A count-down output variable is created by a non-2 gate (27) linked to a first flip-flop's (FFF) (31) output variable (Q) for generating an inverted output variable (Q1). A set output variable (SOV) for a second flip-flop triggers a SOV (S2) for the FFF.