Half subtractor circuit based on ternary and quaternary logic combines input PNP OR-OR dual gates, with a arithmetically linked binary gates and a final ternary stage

摘要

Half subtractor (35) circuit comprises two PNP OR-OR dual gates (9), at the outputs of which are arithmetically linked binary gates (5, 7). The outputs of these are linked to a final ternary stage (17). The input to the first gate is a signal (A1) equal to the count value minus the minuend. The input to the second gate (B1) is equal to the count value minus the subtrahend.