Method and structure for shallow trench isolation during integrated circuit device manufacture

摘要

A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises etching through silicon nitride and pad oxide layers and into a semiconductor wafer to form a trench into the wafer. A shallow trench isolation (STI) layer is formed in the opening in the silicon nitride and in the trench in the wafer which will, under certain conditions, form with an undesirable void. The silicon nitride and pad oxide layers are removed, then an epitaxial silicon layer is formed on the silicon wafer between the STI. A gate/tunnel oxide layer is formed on the epitaxial silicon layer, then a word line is formed over the gate/tunnel oxide. The epitaxial silicon layer ensures that some minimum distance is maintained between the gate/tunnel oxide and the void in the STI. Wafer processing may then be continued to form a completed semiconductor device.