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TEST FACILITATION DESIGNING APPARATUS AND TEST FACILITATION DESIGNING METHOD

机译:试验设施设计装置和试验设施设计方法

摘要

A test facilitation designing apparatus and a test facilitation designing method wherein multiple input/multiple output modules are also classified in type to further advance the test facilitation design. An integrated-circuit test facilitation designing apparatus (1), which facilitates the tests of data paths in an RTL circuit, comprises a pre-processing part (31) that classifies multiple input/multiple output circuit elements, which are part of the circuit elements constituting the data paths, according to a plurality of types as distinguished in a predetermined through classification for the output terminals; and a control path generating part (35) that decides, based on the type of the output terminal as classified in type, a path from an external input to an input terminal of a designated circuit element to be tested or a path from an output terminal of a designated circuit element to be tested to an external output.
机译:一种测试便利性设计设备和测试便利性设计方法,其中,还对多个输入/多个输出模块进行了分类,以进一步推进该测试便利性设计。一种便于RTL电路中的数据路径测试的集成电路测试便利性设计设备(1),包括预处理部分(31),该预处理部分对作为电路元件一部分的多个输入/多个输出电路元件进行分类。根据以预定的通过分类对输出端子进行区分的多种类型来构成数据路径;控制路径生成部(35),根据分类的输出端子的类型,决定从外部输入到要测试的指定电路元件的输入端子的路径或从输出端子的路径将要测试的指定电路元件连接到外部输出。

著录项

  • 公开/公告号WO2007110939A1

    专利类型

  • 公开/公告日2007-10-04

    原文格式PDF

  • 申请/专利权人 SYSTEM JD CO. LTD.;DATE HIROSHI;

    申请/专利号WO2006JP306416

  • 发明设计人 DATE HIROSHI;

    申请日2006-03-29

  • 分类号G06F17/50;

  • 国家 WO

  • 入库时间 2022-08-21 20:47:47

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