METHOD FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, SYSTEM FOR ANALYZING LAYOUT OF SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE, STANDARD CELL LIBRARY, MASK AND SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE

摘要

Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.