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JUNCTION FET

机译:结型场效应管

摘要

PROBLEM TO BE SOLVED: To solve the problems of a conventional junction FET that a channel region surrounded by an insulation region is a single continuous region so that desired mutual conductance gm is obtained around a gate region and that if an impurity concentration with sufficient pinch-off when turned OFF is selected, a pn junction withstand voltage between the channel region and a p-type semiconductor layer is too high to release electrostatic energy, resulting in breakage of an element region before the pn junction breaks down.;SOLUTION: A gate region is provided in a first n-type impurity region, and a source region and a drain region are respectively provided in a second n-type impurity region. Impurity concentrations of the first and second n-type impurity regions can be independently selected. Thus, the impurity concentrations can be independently controlled to obtain the desired mutual conductance gm and desired electrostatic withstand voltage can be obtained without influencing each other.;COPYRIGHT: (C)2009,JPO&INPIT
机译:要解决的问题:为了解决常规结型FET的问题,被绝缘区包围的沟道区是单个连续区,以便在栅极区周围获得所需的互导gm,并且如果杂质浓度足够小,当选择断开断开,pn结承受沟道区域和p型半导体层之间的电压过高的pn结击穿之前释放静电能量,从而导致在元件区域的破损;解:栅在第一n型杂质区域中提供区域,并且在第二n型杂质区域中分别提供源区域和漏区域。可以独立地选择第一和第二n型杂质区域的杂质浓度。因此,可以独立地控制杂质浓度以获得所需的互导gm,并且可以在不相互影响的情况下获得所需的静电耐受电压。;版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP2009158594A

    专利类型

  • 公开/公告日2009-07-16

    原文格式PDF

  • 申请/专利号JP20070332736

  • 发明设计人 IKEDA YOICHI;

    申请日2007-12-25

  • 分类号H01L21/337;H01L29/808;

  • 国家 JP

  • 入库时间 2022-08-21 19:45:32

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