TECHNOLOGY FOR IMPLEMENTING ATOMIC COMPARE AND SWAP INSTRUCTION USING SPECIFIC PROCESSOR

摘要

PROBLEM TO BE SOLVED: To solve the problem that a technology for implementing an atomic compare and swap instruction is required for a CELL processor where a first processor and a second processor have different sized register lines.;SOLUTION: An atomic compare and swap (CAS) operation is mounted in a processor system having a first processor and a second processor. Memory transfer capabilities are different in memory access size between the first processor and the second processor. The first processor specifies the second processor to perform the CAS operation on an address in a main memory. The address has a size less than or equal to a maximum memory transfer size for the second processor and greater than a maximum memory transfer size for the first processor. The second processor atomically performs the CAS operation and notifies the first processor of the success or failure of the CAS operation.;COPYRIGHT: (C)2009,JPO&INPIT