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Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same
Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same
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机译:控制流水线模数转换器的方法和实现该方法的流水线模数转换器
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摘要
Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.
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