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High speed adder design for a multiply-add based floating point unit
High speed adder design for a multiply-add based floating point unit
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机译:基于乘法加法的浮点单元的高速加法器设计
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摘要
An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
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