首页>
外国专利>
Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
展开▼
机译:使用标准图案图块和自定义图案图块来生成具有深阱结构的半导体设计布局,以路由体偏置电压
展开▼
页面导航
摘要
著录项
相似文献
摘要
A semiconductor design layout having a deep well structure for routing body-bias voltage is generated using standard pattern tiles and custom pattern tiles. These tiles have a tile shape and a tile size that fit an integer number of times into a grid unit of a grid for the semiconductor design layout.
展开▼