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Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
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机译:支持集成电路中IP内核实例约束的芯片级集成的通用方法
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摘要
A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
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