首页> 外国专利> SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING A DISTRIBUTED TEST FOR AN ACTIVE BANK IN A BANK SIMULTANEOUS TEST MODE

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING A DISTRIBUTED TEST FOR AN ACTIVE BANK IN A BANK SIMULTANEOUS TEST MODE

机译:能够在银行同时测试模式下对活动银行进行分布式测试的半导体存储器

摘要

PURPOSE: A semiconductor memory device is provided to measure exact data in a bank simultaneous test by performing an active operation according to each bank group.;CONSTITUTION: A bank group control signal generating unit(60) generates plural bank group control signals in response to a bank division test signal and a bank group information signal in a bank simultaneous test mode. A bank address decoding unit(10) generates an internal bank address signal by decoding a bank address in a normal mode. Plural bank active control units(20A) generate plural bank active signals corresponding to each bank group in response to a bank simultaneous test signal, a corresponding bank group control signal and an internal active command signal in the bank simultaneous test mode. The bank active control unit generates plural bank active signals corresponding to each bank(50) in response to the internal bank address signal and the internal active command signal. A plurality of bank pre-charge control units(30) generates plural bank pre-charge signals corresponding to each bank in response to the internal bank address signal, an internal pre-charge command signal and the bank simultaneous test signal. An RAS active signal generating unit(40) generates a plurality of RAS active signals corresponding to each bank in response to the plural bank active signals and the plural bank pre-charge signals.;COPYRIGHT KIPO 2010
机译:用途:提供一种半导体存储器件,以通过根据每个存储体组执行主动操作来测量存储体同时测试中的精确数据;组成:存储体组控制信号生成单元(60)响应于多个存储体组控制信号生成多个存储体组控制信号在存储体同时测试模式下的存储体划分测试信号和存储体组信息信号。存储体地址解码单元(10)通过在正常模式下对存储体地址进行解码来生成内部存储体地址信号。在存储体同时测试模式下,多个存储体有源控制单元(20A)响应于存储体同时测试信号,对应的存储体组控制信号和内部有源命令信号,生成与每个存储体组相对应的多个存储体有源信号。存储体激活控制单元响应于内部存储体地址信号和内部激活命令信号,生成与每个存储体(50)相对应的多个存储体激活信号。多个存储体预充电控制单元(30)响应于内部存储体地址信号,内部预充电命令信号和存储体同时测试信号,生成与每个存储体相对应的多个存储体预充电信号。 RAS激活信号生成单元(40)响应于多个存储体激活信号和多个存储体预充电信号,生成与每个存储体相对应的多个RAS激活信号。COPYRIGHTKIPO 2010

著录项

  • 公开/公告号KR20090126616A

    专利类型

  • 公开/公告日2009-12-09

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20080052782

  • 发明设计人 KIM DONG KEUN;

    申请日2008-06-04

  • 分类号G11C8/12;G11C29/00;

  • 国家 KR

  • 入库时间 2022-08-21 18:33:54

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