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Linear address expansion and mapping to physical memory using 4 and 8 byte page table entries on 32-bit microprocessors
Linear address expansion and mapping to physical memory using 4 and 8 byte page table entries on 32-bit microprocessors
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机译:使用32位微处理器上的4和8字节页表条目进行线性地址扩展并映射到物理内存
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摘要
A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.
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