Code Construction for Error Control in Byte Organized Memories in Microprocessor Systems

摘要

The construction of microcomputer memory systems and error mechanisms are reviewed. Techniques for construction of circuitries for single-error-correcting and double-error-detecting with module-error-detecting capabilities are discussed. New error correcting codes are proposed, which may efficiently be applied to microcomputer memories. These codes allow reduction of logic, and thus reduction of delay, and are suitable for integrated circuit techniques.