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Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout
Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout
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机译:使用建议的解决方案来加快仿真和校正集成电路布图的过程
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摘要
One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.
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