A method and semiconductor device with a protective layer for reducing the stress relaxation in a double bracing coating art

摘要

A method with:Forming a first dielectric bracing induzier ends, layer (310) by means of a p - channel transistor (350b) and an n - channel transistor (350a);selective removal of a region of the first bracing induzier ends layer (310) of the p - channel transistor (350b);Forming a second dielectric bracing induzier ends layer (320) by means of the p - channel transistor (350b) and the n - channel transistor (350a);selective removal of a region of the second bracing induzier ends layer (320) of the n - channel transistor (350a);Forming a dielectric buffer layer over the first bracing induzier ends dielectric layer (310) by means of a first deposition process (311) without plasma assistance in front of the selective removal of a region of the first bracing induzier ends layer (310) of the p - channel transistor (350b);Forming an etching expensive layer (304) on the dielectric buffer layer before the form of the second bracing induzier ends layer (320), wherein the etching expensive layer by a second deposition process (313) is formed, which of the first deposition process (311); and wherein the selective removal of the region of the second bracing induzier ends layer (320) includes: performing of an etching process, and using the..