TEST DESIGN SUPPORT DEVICE AND TEST DESIGN SUPPORT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit test design support device capable of creating a test pattern preventing malfunction of a chip even when simultaneously operating functional blocks on the chip in a range wider than actual operation.;SOLUTION: A semiconductor integrated circuit test design support device comprises: an IR drop analysis unit for operating a functional block independently and executing an IR drop analysis; a mapping value creation unit for calculating an IR drop amount Z, which is quantized by each address (X, Y) showing each small region on a chip, and creating a mapping value (X, Y, Z); and a grouping unit for calculating the mapping value (X, Y, Z) when operating the functional block in a plural manner by adding the quantized IR drop amount Z of the same address (X, Y), and for, if the quantized IR drop amount Z of the address (X, Y) when simultaneously operating the functional blocks is within an acceptable value, grouping the functional block into simultaneously operable functional blocks.;COPYRIGHT: (C)2012,JPO&INPIT