Stress reduction on vias and yield improvement in layout design through auto generation of via fill

摘要

A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.