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STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS
STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS
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机译:制作晶格错位源和漏区的应变半导体CMOS晶体管的结构和方法
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摘要
A p-type field effect transistor (PFET) (10) and an n-type field effect transistor (NFET) (12) of an integrated circuit are provided. A first strain is applied to the channel region (20) of the PFET (10) but not the NFET (12) via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions (111) of only the PFET (10) and not of the NFET.(12) A process of making the PFET (10) and NFET (12) is provided. Trenches are etched in the areas to become the source and drain regions (111) of the PFET and a lattice-mismatched silicon germanium layer (121) is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon (14) can be grown over the silicon germanium layer (121) and a salicide (68) formed from the layer of silicon to provide low-resistance source and drain regions (111).
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