Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

摘要

We explore several technology options for the enhancement of electron and hole mobility in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, focusing on strain engineering using lattice-mismatched source/drain (S/D) materials. Silicon-carbon (Si_(1-y)C_y) and silicon-germanium (Si_(1-x)Ge_x) have lattice constants different from that of the Si channel. When Si_(1-y)C_y or Si_(1-x)Ge_x is embedded in the transistor S/D region, lateral tensile or compressive strain is induced in the adjacent Si channel, leading to improvement in the electron or hole mobility, respectively. The origin of the strain effect, process integration, device characteristics and strain enhancement approaches are discussed.