首页> 外国专利> SOLVING METHOD OF A SUBSTRATE WARPAGE PROBLEM DUE TO HEAT EXPANSION CONTRACTION RATE DIFFERENCE CAPABLE OF PREVENTING THE DAMAGE OF THE SUBSTRATE AND AN ELECTRONIC COMPONENT BUILT-IN PRINTED CIRCUIT BOARD APPLYING THE METHOD

SOLVING METHOD OF A SUBSTRATE WARPAGE PROBLEM DUE TO HEAT EXPANSION CONTRACTION RATE DIFFERENCE CAPABLE OF PREVENTING THE DAMAGE OF THE SUBSTRATE AND AN ELECTRONIC COMPONENT BUILT-IN PRINTED CIRCUIT BOARD APPLYING THE METHOD

机译:能够防止基体损伤的热膨胀收缩率差异的基体翘曲问题的解决方法和采用该方法的电子部件内置电路板

摘要

PURPOSE: A solving method of a substrate warpage problem due to heat expansion contraction rate difference and an electronic component built-in printed circuit board applying the method are provided to prevent a warpage occurrence of the substrate by using a laminate-molded material in which maintaining more than 50% of the content of the ceramic filler.;CONSTITUTION: A cavity is manufactured in an internal layer insulating layer(180) of a hardened status. An electronic component(170) is built in the cavity. A first insulation layer and a copper foil(190) of a semi-hardened status are laminated on the electronic component. A via hole is formed after the first insulation layer is solidified. The via hole electronically connects the copper foil of the substrate outside layer and an input-output terminal bump of the electronic component.;COPYRIGHT KIPO 2013
机译:用途:解决由于热膨胀收缩率差异引起的基板翘曲问题的方法和应用该方法的电子部件内置印刷电路板,以通过使用其中保持有光泽的层压成型材料来防止基板翘曲的发生。大于陶瓷填料含量的50%。;组成:在硬化状态的内层绝缘层(180)中制造了一个空腔。在腔体中内置有电子部件(170)。在电子部件上层叠有第一绝缘层和半硬化状态的铜箔(190)。在第一绝缘层固化之后形成通孔。通孔将基板外层的铜箔与电子元件的输入输出端子凸点电连接。COPYRIGHTKIPO 2013

著录项

  • 公开/公告号KR101253514B1

    专利类型

  • 公开/公告日2013-04-11

    原文格式PDF

  • 申请/专利权人 APERIO CO. LTD.;

    申请/专利号KR20110110637

  • 发明设计人 KIM KI HUN;KO YOUNG JOO;

    申请日2011-10-27

  • 分类号H05K3/46;H05K1/02;H05K1/18;

  • 国家 KR

  • 入库时间 2022-08-21 16:25:24

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