ACTIVITY CORRELATION BASED OPTIMAL CLUSTERING FOR CLOCK GATING FOR ULTRA-LOW POWER VLSI

摘要

A clustering bus-specific clock gating method is described to reduce the dynamic power consumed by redundant clock ticks in gate-level. The method exploits correlations between flip-flops for clock gating. An activity correlation matrix is introduced to describe the correlations between the flip-flops. Based on activity correlation information, the flip-flops are classified into several clusters. A payoff function is also described to find an optimal classification scheme. Based on the classification strategy, flip-flop clusters that are less active and more correlated will be gated.