Random Generator semi-Markov process with a symmetrical law of distribution

摘要

The invention relates to the field of computer technology and can be used in constructing simulation models of systems operating under the conditions of random disturbances, configuration and operation of various control devices.;The technical result obtained in this technical decision is simplification of a semi-Markov random process generator by reducing the number of memory cell blocks, wherein the specified duration of simulated random process, and a 2-fold reduction of the bit.;The technical result is achieved in that the random generator semi-Markov process with symmetric distribution laws comprising timing unit, a first output of which is connected to an input of synchronization of the first memory register, the output of which is the output of the generator, memory, a first register output connected to a data input of the second memory register output which is connected to the first address input of the first memory block, a second address input connected to the output of the third memory register, the information whose input is connected to the output of the sensor is uniformly distributed random numbers, the first memory unit output is connected to the data input of the first memory register, three keys OR-NO element, the second memory unit, the counter, key unit, an OR gate, a first input coupled to the second output sync block, output of OR element connected to the input "Poll" sensor uniformly distributed random number whose output is connected to data input key unit, the counter, the count input of which is connected to the first input sync block ronizatsii, the counter output is connected to an input of OR-NO element whose output is connected to the control inputs of the first, second and third key information inputs of the first and second switch are coupled and connected to the third input of the synchronization unit, fourth output of which is connected to the data input of the third switch, whose output is connected to the third memory register synchronization input, the first switch output connected to a second input of the aND gate, the second switch output is connected to the control input of the key input unit and to sync ii second memory register, introduced an adder-subtractor, the output of which is connected to the data input of the counter, and a control input coupled to the high bit key block, the first input of the adder-subtractor connected to the output of the storage unit and the second input is the input of the generator, through which is introduced the required duration of the average value of intervals. 1 yl.