METHOD FOR IMPLEMENTING AN INTEGRATED DEVELOPMENT ENVIRONMENT (IDE) FOR DESIGN, MODELING AND ANALYSIS OF VLSI CIRCUITS

摘要

The various embodiments of the present invention disclose a method for implementing an Integrated Development Environment tool with a simplified and easily accessible architecture. The method comprises selecting a coding model for creating a new project, optimizing a code logic, synthesizing a netlist for the optimized code logic, placing the standard cell and viewing the placed cells, routing a placed cell design, extracting the netlist, comparing the netlist, visualizing a real layout and converting the layout of the compared netlist into a Geometric data stream (GDS) file or Caltech Intermediate Format (CIF) file. The selection is done among a Verilog model, a VHSIC Hardware Description Language (VHDL) model and a Finite State Machine (FSM) model.