首页>
外国专利>
Handling of error prone cache line slots of memory side cache of multi-level system memory
Handling of error prone cache line slots of memory side cache of multi-level system memory
展开▼
机译:多级系统内存的内存侧缓存的容易出错的缓存行插槽的处理
展开▼
页面导航
摘要
著录项
相似文献
摘要
An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
展开▼