首页>
外国专利>
GATE STACK DESIGN FOR GAN E-MODE TRANSISTOR PERFORMANCE
GATE STACK DESIGN FOR GAN E-MODE TRANSISTOR PERFORMANCE
展开▼
机译:用于GAN E模式晶体管性能的栅极堆叠设计
展开▼
页面导航
摘要
著录项
相似文献
摘要
A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.
展开▼