NOVEL METHOD TO COMPUTE TIMING YIELD AND YIELD BOTTLENECK USING CORRELATED SAMPLE GENERATION AND EFFICIENT STATISTICAL SIMULATION

摘要

Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.