SRAM MEMORY WITH IMPROVED READ END TRIGGER

摘要

Circuit (10) triggering the end of read operation, for SRAM memory device, comprising: - a plurality of pairs of transistors (14a, 14b) connected to a bit line (BLTi,) and a complementary bit line (BLFi ), the transistors each having a source connected to a node (12), the node (12) and the bit lines being, prior to the activation of said given word line, respectively preloaded by means of preload, then, when said word line is activated, at least the bit lines are disconnected from the preload means, so as to modify the conduction state of certain transistors and consequently cause a variation in potential of said node up to 'to reach a determined threshold potential triggering the emission of the end of phase signal (Seor).