A cryogenic phase locking loop system for a superconducting integrated receiver

摘要

The authors present a new cryogenic device, an ultrawideband cryogenic phase locking loopsystem (CPLL). The CPLL was developed for phase locking of a flux-flow oscillator (FFO) in asuperconducting integrated receiver (SIR) but can be used for any cryogenic terahertz oscillator.The key element of the CPLL is the cryogenic phase detector (CPD), a recently proposed newsuperconducting element. The CPD is an innovative implementation of a superconductor-insulator—superconductor tunnel junction. All components of the CPLL reside inside a cryostatat 4.2 K, with the loop length of cables 50 cm and the total loop delay 4.5 ns. So small a delayresults in a CPLL synchronization bandwidth as wide as 40 MHz and allows phase locking ofmore than 60% of the power emitted by the FFO, even for FFO linewidths of about 11 MHz.This percentage of phase locked power is three times that achieved with conventional roomtemperature PLLs. Such an improvement enables reducing the FFO phase noise and extendingthe SIR operation range.