A HIERARCHICAL SMART-PIXEL ARRAY FOR FEATURE EXTRACTION WITH ON-CHIP STORAGE

摘要

In this paper we present a new paradigm of hierarchical smart-pixel arrays together with an example for feature extraction and compressed on-chip storage of the input pattern. A prototype with 16 X 16 pixels has been designed and tested. It consists of two different types of cells which are arranged in hierarchical layers similar to a quadtree structure. Main features of this prototype are edge detection and simplified on-chip storage of the optical input pattern. [References: 4]