Small matters: Rethinking electronic component design approach and the benefit that lies within

摘要

Electronic components used in the manufacture of electronic products are presently available in a wide variety of different sizes, shapes and formats. Electronic component catalogs are filled with page after page of offerings for both passive and active devices including both through hole and surface mount variations. JEDEC (Joint Electronic Device Engineering Council) under the aegis of its JC-11 committee oversees the registration of mechanical outlines of all electronic packaging. In the work of JC-11.11 which targets specifically microelectronic plastic packages, there are more than 80 different standards for such packaging. Understanding the lexicon and terminology of standardized IC packaging can be quite challenging. Looking at just the matter of IC package thickness or package profile, one will find the following descriptions with their associated designators: low (L), thin (T), very thin (V), very very thin (W), ultra thin (U), extra thin (X1) and super thin (X2), paper thin (X3) and die thin (X4). Figure 1 provides a graphic to illustrate the differences. Interestingly, the same "80% rule" that was applied to lead pitch was adopted One must also keep in mind the different package and lead formats (BGA, CSP, DIP, FBGA, LGA, QFN, QFP, SIM, SIP, SOT, TSOP-1, TSOP-2, WLP, ZIP, etc.) with outlines identified for the different lead counts which can run from 3 to 3000 or more. There are as well, many different lead pitches (2.54, 1.27, 1.0, 0.8, 0.65, 0.5, 0.4, 0.3, 0.250 mm). Finally, there are also registered dual pitch components, dual lead type components and stackable components. It doesn't take a background in mathematics to realize that the number of potential package variations can run into the many thousands.