Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. The difficulty comes from the existence of memory elements. With memory elements, such as latches or flip-flops, the circuit output depends not only on the current inputs but also on the operation history (circuit states). Of course, it is possible to facilitate sequential circuit testing by adding some extra hardware, which enhances the controllability and observability of the circuit. However, the test hardware increases hardware overhead and can degrade circuit performance. Thus, before using valuable chip space, test generation without adding extra hardware should be tried.
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