A Proposed DLCCS Algorithm for High Speed Operation & Implementation on FPGA

摘要

In the modern era of electronics and communication, the basic logic operations like addition of multiple data(s), followed by integrating those multiple adder(s) to design complex analog/digital circuits using VLSI technology requires low power, less area and high speed constrains. This paper depicts the objective to design a very fast adder to solve various operations starting from the basic combinational circuits to n~(th) higher order complex mathematical functions. The proposed D Latched Conditional Carry Selection (DLCCS) algorithm is proposed to design the fastest adder after a thorough analysis of various adder(s) using Xilinx 1SE 14.2. Firstly, Orthodox Carry Select Adder (OCSLA) using Ripple Carry Adder (RCA) is designed and simulated. OCSLA with pipelining (PCSLA) structure can provide low power and comaparative less area but due to usage of each 2 bit Full Adders the pad to pad delays get increased which is undesired. On the other hand, the OCSLA area is about as twice as that of the RCA, for a given bit-width. The ADD ONE Carry Select Adder (A1CSLA) relies on optimizing the OCSLA by replacing the adder with C_(IN)=1 by a less expensive logic, known as "ADD-ONE logic", where a significant amount of reduction in path delay has been observed. The regular CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial' sum and carry. To overcome the above problem, the regular CSLA is modified by using n-bit Binary to Excess-1 Code converters (BEC) to improve the speed of addition. Though, in BE1 CSLA the major limitation is that due to don't care condition there may be some mismatch in desire output. In our proposed DLCCS algorithm based adder, the BEC is replaced by a D-Latch. Initially when CLK=1, the output of the RCA is fed as input to the D-Latch and the output of the D-latch follows the input and given as an input to the multiplexer. When CLK=0, the last state of the D input is trapped and held in the latch and therefore the output from the RCA is directly given as an input to the multiplexer without any delay. Now the multiplexer selects the sum bit according to the input carry which is the selection bit and the inputs of the multiplexer are the outputs obtained when CLK=1 and 0. Thus the proposed DLCCS algorithm based CSLA is implemented by Verilog source coding, followed by simulation and synthesis. Significant amount of less power and high speed is obtained after FPGA implementation. All the designing of adder(s) is done using Xilinx 1SE 14.2 and synthesized successfully in the FPGA Virtex 6 target device operated at 64.516 MHz clock frequency.