A JFET device for CMOS integrated circuits and its application to CMOS-based low noise amplifiers

摘要

In this paper, a fabrication technology of JFET integration in standard CMOS is presented. JFET is used in CMOS (operational) amplifiers for realization of very low-noise sensor interface circuits. JFET devices are formed with "well" structures in standard CMOS circuits. In a p-well region, n-type channel is formed by deep P ion-implantation with energy of 150 keV to connect n+ source and drain region already formed. After that, p-type top gate is formed by B ion-implantation with energy of 30 keV. Fabricated JFFT devices showed larger transconductance as compared to MOSFET devices formed on the same die. Noise power-spectrum of fabricated JFET was also evaluated, and very low-level noise amplitude was observed.