Suppression of Degradation Induced by Negative Gate Bias and Illumination Stress in Amorphous InGaZnO Thin-Film Transistors by Applying Negative Drain Bias

摘要

The effect of drain bias (V_(DS)) on the negative gate bias and illumination stress (NBIS) stability of amorphous InGaZnO (a-IGZO) thin-film transistors was investigated using a double-sweeping gate voltage (V_(GS)) mode. The variation in the transfer characteristics was explored using current—voltage and capacitance—voltage characteristics. In the initial stage (<1000 s) of NBIS with grounded V_(DS0 (V_(GS) = —40 V and V_(DS) = 0 V), the transfer characteristics shifted negatively with an insignificant change in the subthreshold swing (SS) because of hole trapping at an IGZO/gate insulator interface. On the other hand, on-current degradation was observed and was accelerated in the forward measurement as the NBIS duration increased. The results indicated that NBIS induced donor-like defects near the conduction band; however, the transfer curves in the reverse measurement shifted positively without on-current and SS degradations. It was found that the degradations were enhanced by applying a positive V_(DS) bias (V_(GS) = —40 V and V_(DS) = 40 V); in contrast, they could be reduced by applying a small negative V_(DS) of V_(DS) >V_(GS) (V_(GS) =-40 V and V_(DS) =-20 V). Furthermore, it was confirmed that the NBIS degradations could be suppressed by applying a large negative V_(DS) bias of V_(DS) < V_(GS) (V_(GS) = —40 V and V_(DS) = —60 V) during NBIS.