Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit

摘要

Operating a Graphics Processing Unit (GPU) at Near Threshold Computing (NTC) domain comes with a significant performance variability as a consequence of process variation (PV). In the emerging era of General Purpose GPUs (GPGPUs), the existence of a large register file is inevitable. In this paper, we investigate increased sensitivity of the GPGPU register file to PV and suggest a dynamic allocation of thread blocks based on register access latency. We further exploit the variation in maximum operating frequencies of cores in a GPU to hide the excessive long access latencies. The proposed technique optimizes GPU energy consumption by ～35% over an ideal PV-free GPU operating at Super Threshold regime. The area and power overhead for Split Latency Allocator are 1.1% and 1.9% respectively.