Design of BCD Compressors Using Vinculum Code for Efficient Multiplication

摘要

Compressors play a very important role in multipliers for adding partial products. Decimal Computations has grown interest in recent years due to the availability in its hardware architectures. In literature binary compressors are available but decimal compressors are not that much exposed. This paper gives a basic principle of 3:2 decimal VBCD compressors with three operands of 4bit each. It uses a binary full adder for adding bits and simple correction circuit. This structure can be used to add partial products in multiplier. This paper presents from a basic 3:2 compressor to 8:2 compressor. The simulation have been carried out in Cadence Digital Encounter TSMC 180nm technology and were compared with decimal compressors.