A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

摘要

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current I-on, while the off current I-off remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher I-on are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%.