Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics

摘要

Multiple-valued logic (MVL) circuits reduce the complexity of connections, thereby decreasing power consumption and chip area. In the recent years, many studies have been conducted on multiple-valued logic due to the high potentials of carbon nanotube transistors in designing these circuits. (MVL) circuits have less noise margin in comparison to the binary ones because of the adjacency of the levels. In this paper, the quaternary logic gates were designed using a novel structure and two separated paths with diode connection to generate '1' and '2' logic levels. This allowed the better adjustment of parameters, increased noise margin, and reduced the power consumption in the '1' and '2' logic levels. A new method was also developed to design quaternary combinational circuits; this method was implemented in the full adder circuit. The designs were simulated using the HSPICE software and the 32 nm Stanford CNTFET model. The simulation results indicated significant improvements in terms of power consumption, PDP, and noise margins in the new model, as compared to the prior works. The PDP improvements were about 79% and 63% for the proposed buffer and SQI gates, respectively, while it was 70% for the quaternary full adder design, as compared to the best single supply-based work reported so far. Also, noise margins were improved in the proposed buffer, getting close to an ideal noise margin of about Vdd/6. (C) 2019 Elsevier GmbH. All rights reserved.