Super-cell design based on statically substrate-biased domino CMOS circuit: combinational logic cell with continuously variable transistor width

摘要

A statically substrate-based Domino CMOS (SSDCMOS) circuit scheme having the pull-up / pull-down transistors with high threshold voltages, of which the source terminals are only connected to the base of the power supply source and ground, was proposed [1,2,3]. Being based on this circuit, the super-cell layout architecture with a continuously variable transistor width, which corresponds to the load of the output interconnection RC, has been proposed [4]. In this paper, we study the performance of AOI24 logic cell that is designed with the intention of balance on high speed and low power. In this paper, we compare it to its equivalent static CMOS circuit, by using a circuit simulator based on the BSIM3v3 model of 0.35 μm CMOS process. When the width of a rectangular transistor being surrounded by the source terminal is 66 λ (λ = 0.175 μm), the area of AOI24 logic cell can be reduced to 57%, the delay time of that to 94%, and the power consumption to 79%.