A parallelizing compile algorithm in hardware/software cosynthesis system for processor cores with packed SIMD type instruction sets

摘要

Consider to synthesize a processor with packed SIMD type instructions by a hardware/software cosynthesis system. The system needs a parallelizing compiler for the processor with packed SIMD type instructions. The parallelizing compiler targets the virtual processor that has all availabale hardware units. It exploits instruction level parallelism using packed SIMD type instructions and output assembly codes. The output of the parallelizing compiler decides the initial configuration of the processor. This paper proposes a packed SIMD generation algorithm and an instruction merge algorithm. The packed SIMD generation algorithm packs and aligns low precision data in a register and generates packed SIMD type instructions. The instruction merge algorithm merges several packed SIMD type instructions to generate the packed SIMD type instructions that include saturation and shift operation. Experimental results demonstrate effectiveness and efficiency of the algorithm.