An Optimized Design for Parallel MAC Based on Radix-4 MBA

摘要

In this paper a novel architecture of multiplier and accumulator (MAC) for high speed arithmetic is presented. The architecture adopts radix-4 modified booth algorithm (MBA) and hybrid carry save adder, in which the accumulator that has the largest delay in MAC was merged into Carry save adder (CSA) block. The performance of final adder block, which determines critical path of the architecture, is improved by reducing number of input bits of the final adder itself. Moreover the design accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme. Using this architecture the overall performance can be elevated twice that of previous architectures. The proposed design was coded in verilog HDL and simulated using Xilinx ISE tool. FPGA Spartan 3E starter kit was used for implementation of design.