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首页> 外文期刊>Journal of nanoscience and nanotechnology >Vertically Integrated Logic Circuits Constructed Using ZnO-Nanowire-Based Field-Effect Transistors on Plastic Substrates
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Vertically Integrated Logic Circuits Constructed Using ZnO-Nanowire-Based Field-Effect Transistors on Plastic Substrates

机译:在塑料基板上使用基于ZnO-纳米线的场效应晶体管构建的垂直集成逻辑电路

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ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of ~100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I_(ON)/I_(OFF) of > 10~6, with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of ~93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.
机译:基于ZnO纳米线的逻辑电路是通过在塑料基板上垂直集成多层场效应晶体管(FET)来构建的。通过热化学气相沉积法合成了平均直径约为100 nm的ZnO纳米线,用作FET的沟道材料。 ZnO基FET具有大于10〜6的高I_(ON)/ I_(OFF),具有n型耗尽模式的特性。对于垂直集成逻辑电路,依次准备了三个多层FET。堆叠的FET经由电极串联连接,并且C-PVP被用作层隔离材料。非门与与非门的逻辑摆幅较大,约为93%。这些结果证明了三维柔性逻辑电路的可行性。

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