A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive

摘要

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented,and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects.In this work,one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures.Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains.Evaluation results of the wafer bonding,which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive,are also presented through the wafer bonding between a glass wafer and a silicon wafer.After wafer bonding,three evaluations are conducted;(1) the fraction of bonded area is measured through the optical inspection,(2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade,and (3) the quantitative bond strength is measured by a four point bending.To date,benzocyclobutene (BCB),Flare~(TM) meth-ylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives.Of the candidates,BCB and Flare~(TM) were determined as adhesives after screening tests.By comparing BCB and Flare~(TM),it was deduced that BCB is better as a baseline adhesive.It was because although wafer pairs bonded using Flare~(TM) has a higher bond strength than those using BCB,wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k inter-level dielectrics (TLD),indicating almost 100% of bonded area routinely.