Circuits design of memory accessing system based on AXI interface

摘要

This paper proposes a method for designing the DDR3 SDRAM (Double Data Rate3 Synchronous Dynamic Random Access Memory) memory accessing system based on AXI (Advanced eXtensible Interface) interface, which can achieve data transmission between SoC (System on-Chip) and off-chip SDRAM through AXI interface complying with AXI protocol. The whole design has been accomplished by using Verilog hardware description language, and the functional simulation has been done in Modelsim10.0a software tool. Three different parameters, including bandwidth, delay and the size of buffer FIFO (First In First Out) have been analysed in the proposed system. Through FPGA (Field Programmable Gate Array) on-board verification, this DDR3 memory accessing system can operate at 200MHz well.