Interconnect Metrology Confidently Looks at 32 nm

摘要

As the pursuit of Moore's Law forced the dominance of interconnect delay over gate delay, aluminum gave way to copper's lower resistivity. This introduced a new deposition process, dual damascene, where the dielectric is patterned before the metal and coated with liner and seed layers to protect the copper and facilitate deposition. The copper is electrochemically deposited to fill these trenches and holes, followed by chemical mechanical planarization (CMP) and a dielectric cap on the resulting surface to protect it. The process worked, but the need to keep it in spec brought metrology to center stage.