A 120-GHz Bandwidth CMOS Distributed Power Amplifier With Multi-Drive Intra-Stack Coupling

摘要

This letter presents a distributed power amplifier (DPA) topology that improves both the power combining efficiency and the operation bandwidth. Multi-drive intra-stack coupling is introduced in the design of the gain cells to break the tradeoff between high output power ( $P_{ext {OUT}}$ ) requirement and the achieved bandwidth. The proposed technique also compensates for the input transmission line (TL) loss to accommodate more stages and achieve flat gain and higher $P_{ext {OUT}}$ . A prototype eight-stage, 16-dB gain, 120-GHz bandwidth DPA is fabricated in 45-nm CMOS silicon-on-insulator (SOI) using elevated coplanar waveguide (CPW) TLs with a core area of 0.51 mm^{2. The amplifier maintains an output $P_{mathrm {1,dB}}$ and $P_{mathrm {SAT}}$ higher than 18 and 20 dBm, respectively, up to 60 GHz and achieves a peak PAE of 19.7% at 15 GHz. A 64-quadrature-amplitude modulation (QAM) modulated signal with data rate 30 Gb/s (5 GBaud/s) is demonstrated at 55 GHz with a 13.5 dBm average $P_{mathrm {OUT}}$ and 6.9% PAE while the error vector magnitude (EVM) is kept below 5%. To the authors’ knowledge, the achieved 757-GHz gain-bandwidth product (GBW) is the highest among reported non-cascaded DPAs. The DPA has also the highest continuous-wave (CW) and modulated PAE compared to other reported distributed amplifiers (Das).}